In this post, we will see how to resolve Vivado not allowed me to build project due to [DRC NSTD-1] Question: I have the issue like this: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 10 logical ports use I/O ...
Question: I’m trying to convert some code from Verilog to VHDL for project need. The original code is in Verilog, the aim of the code is to realizing MIG DDR2/3 write and read, partly shown as following: and here is ...
Question: I am new to Vivado HLS ( using Vivado HLS 2018.3 ). I am writing this code to generate a 16-bit CRC (Cyclic Redundancy Check) using a 128-bit message and 17-bit generator polynomial. Here in the source code, I ...
Question: I have a FSM consisting of 3 states: STATIC, UP and DOWN. The FSM starts in the STATIC state and if I press the up arrow key, it will move to the UP state, thereafter returning to the STATIC ...
Question: I try to create IP Block in vivado and launch SDK but Launch SDK does not appear file menu. 1-I create a project and I choice the zedboard Zynq Evaluation Board 2-I create a block design and I add ...